1. Field of the Invention
The preset invention relates to a solid state image pickup device and a camera provided with a solid state image pickup device.
2. Related Background Art
Up to now, CCDs have been widely employed as solid state image pickup devices because of their high SN ratios. Meanwhile, development of a so-called amplification type solid state image pickup device is under way, the device excelling in low power consumption and high usability. The amplification type solid state image pickup device is configured such that signal charges accumulated in a photodiode are introduced to a control electrode of a transistor in each pixel and an electric signal according to a signal charge amount is amplified and output from a main electrode of the transistor. In particular, a so-called CMOS sensor employing a MOS transistor as a transistor well matches a CMOS process and enables on-chip driver circuit and signal processing circuit. Accordingly, development of the CMOS sensor is being eagerly pursued.
FIG. 5 is a circuit diagram showing a typical example of a CMOS sensor pixel. In FIG. 5, reference numeral 1 denotes a unit pixel; 2, a photodiode for accumulating signal charges generated due to incident light; 3, an amplifying MOS transistor for outputting an amplified signal according to a signal charge amount; 4, a floating diffusion (hereinafter, referred to as “FD”) region receiving the signal charges and connected with a gate electrode of the amplifying MOS transistor 3; 5, a MOS transistor for transferring the signal charges accumulated in the photodiode 2 to the FD region 4; 6, a resetting MOS transistor for resetting the FD region 4; 7, a selecting MOS transistor for selecting an output pixel; 8, a control line for applying pulses to a gate of the MOS transistor 5 and controlling a charge transferring operation; 9, a control line for applying pulses to a gate of the resetting MOS transistor 6 and controlling a resetting operation; 10, a control line for applying pulses to a gate of the selecting MOS transistor 7 and controlling a selecting operation; 11, a power supply line connected to a drain of the amplifying MOS transistor 3 and a drain of the resetting MOS transistor 6 and supplying a power supply potential to the transistors; 12, an output line to which an amplified signal of the selected pixel is output; 13, a constant-current MOS transistor operating as a constant current source and constituting a source follower in corporation with the amplifying MOS transistor 3; and 14, a wiring for supplying to a gate electrode of the constant-current MOS transistor 13 such a potential as allows for a constant-current operation of the constant-current MOS transistor 13. The unit pixels 1 are two-dimensionally arranged in a matrix shape to constitute a pixel region of a two-dimensional solid state image pickup device. In such matrix arrangement, the output line 12 serves as a common line for pixels in respective columns, and the control lines 8, 9, and 10 serve as common lines for pixels in respective rows. Signals from the pixels in a row selected by the control line 10 are only output to the output line 12.
Next, an operation of the pixel is explained in brief. For the pixels in the row where the selecting MOS transistor is turned ON by the control line 10, a pulse is first applied to the control line 9 to reset the FD region 4. The amplifying MOS transistor 3 and the constant-current MOS transistor 13 constitute a source follower. Thus, an output potential according to a reset potential appears in the output line 12. Next, when the signal charges accumulated in the photodiode are transferred to the FD region 4 by applying a pulse to the control line 8, a potential of the FD region 4 changes by a voltage according to the signal charge amount. The potential change is reflected in the output line 12. The reset potential appearing in the output line 12 involves a threshold voltage variation of the amplifying MOS transistor 3, and noise such as reset noise generated in resetting the FD region 4. In light of this, the potential change according to the signal charge amount corresponds to a noise-free signal. In the two-dimensional CMOS sensor, the output line 12 is connected with a read-out circuit for eliminating the noise and taking out only a signal. With regard to the read-out circuit, some structures are proposed including one where the noise is eliminated with a clamp circuit, and one where the noise is eliminated by separately holding noise and (noise+pure signal), and introducing each to a differential amplifier at the final stage during horizontal scanning (reading). However, such structures do not directly relate to the present invention, and hence a detailed description thereof is omitted here.
Next, a sectional structure of a portion corresponding to the photodiode and amplifying MOS transistor of the pixel is shown in FIG. 6. In FIG. 6, reference numeral 15 denotes an N-type semiconductor substrate; 16, a P-type well; and 17, an N-type semiconductor region which is formed in the P-type well 16, constitutes a photodiode together with the P-type well 16, and accumulates signal charges generated due to incident light. Denoted by 18 and 19 are N-type semiconductor regions formed in the P-type well 16 and serving as a drain and source of the amplifying MOS transistor 3, respectively. Reference numeral 20 denotes a gate electrode of the amplifying MOS transistor 3; 21, a thick oxide film for element isolation, that is, so-called LOCOS; 22, a channel stopper made from a P-type semiconductor layer with the same conductivity type as that of the P-type well 16 and formed directly below the LOCOS 21; 11, a drain wiring connected with the drain 18; and 23, a source wiring connected with the source 19. The signal charges accumulated in the N-type semiconductor region 17 are transferred to the FD region 4 during a transferring operation. An N-type impurity concentration in the N-type semiconductor region 17 is set so as to turn the region into a depletion region just after the transfer.
Japanese Patent Application Laid-open No. 2000-150848 (FIG. 7) discloses a solid state image pickup device where a p-type buried layer is formed at a predetermined depth in an n-type substrate. A photoelectric conversion part is formed in a upper portion of the n-type substrate about the p-type buried layer.
However, the aforementioned conventional CMOS sensor encounters a problem in that so-called 1/f noise is generated from the amplifying MOS transistor 3 to increase a noise level in the entire sensor. Also, in general, the amplifying MOS transistor 3 is operated as a source follower, but the following problem arises here. That is, a potential of the P-type well 16 is set to a fixed value, which drops a gain at the time of source follower operation due to a back gate bias effect, lowering a signal level. The signal charges generated downstream of the photodiode are not always absorbed in the photodiode but are likely to be absorbed in the FD region 4 and the N-type source/drain of the amplifying MOS transistor 3, the resetting MOS transistor 6, and the selecting MOS transistor 7 in the pixels in a certain probability. As discussed above, there is a problem in that the signal charges are absorbed in components except the photodiode, resulting in low sensitivity.
Also, in the pixel structure as disclosed in Japanese Patent Application Laid-Open No. 2000-150848, an amplifying MOS transistor provided in a pixel is formed in a well whose conductivity type is opposite to that of its source/drain. Hence, it is impossible to form a depletion region below a channel formation region unlike the present invention nor to minimize a substrate bias effect to a satisfactory level. Accordingly, the 1/f noise cannot be sufficiently reduced, and the gain of the source follower cannot be designed to be up.